Enhanced highly pipelined bus architecture
US6907487B2 · kind B2 · utility
11Cited by
23References
62Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2001 |
| Grant date | Jun 14, 2005 |
| Priority date | — |
| Expiry date | Aug 17, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4217
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a control interface to drive a control signal at a clock frequency, an address bus interface to drive address elements at twice the clock frequency, and a data bus interface to drive data elements at four times the clock frequency. The address bus interface drives a substantially centered address strobe transition for each address element, and the data bus interface drives a substantially centered data strobe transition for each data element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.