Mapping of interconnect configuration space
US6907510B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2002 |
| Grant date | Jun 14, 2005 |
| Priority date | — |
| Expiry date | Sep 16, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0292
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for accessing a configuration data space for a device connected to a processor through an interconnect includes receiving a request from the processor to access the processor's addressable space. The request is generated in response to receiving an instruction intended to access the device's configuration data space. A map between the device's configuration data space and the processor's addressable space is accessed, the map having previously mapped the device's configuration data space to one or more pages of the processor's addressable space. Using the map, the request from the processor is translated into a configuration cycle on the interconnect to access the device's configuration data space.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.