Semiconductor integrated circuit and its design methodology
US6907585B2 · kind B2 · utility
13Cited by
5References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 10, 2003 |
| Grant date | Jun 14, 2005 |
| Priority date | — |
| Expiry date | Nov 27, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318594
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and device are provided for applying logic BIST at speed for large-scale and high-performance logic circuits without increasing test time, and decreasing test costs as a result. In one example, a logic BIST controller is divided into two portions. A clock signal having a small delay is used to drive a partial circuit that supplies a user circuit with a scan enable signal and a clock signal. A clock signal having a large delay is used to drive a partial circuit that supplies the user circuit with a test pattern and collects a test result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.