System and method for evaluating vias per pad in a package design
US6907589B2 · kind B2 · utility
10Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2003 |
| Grant date | Jun 14, 2005 |
| Priority date | — |
| Expiry date | Jul 18, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and software product evaluate vias, per pad, in an electronic design. One or more via per pad rules are formulated, and then the electronic design is processed to determine whether the vias of the electronic design violate the via per pad rules. In the event of a violation, one or more indicators are generated to identify vias that violate the via per pad rules. The indicators are visual indicators (e.g., via per pad DRCs) on a graphical user interface, and/or a textual report summarizing violations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.