Partial reconfiguration of a programmable logic device using an on-chip processor

US6907595B2 · kind B2 · utility

Assignee

• XILINX, INC. · US

Inventors

• Derek R. Curd · San Jose, US
• Punit S. Kalra · Superior, US
• Richard J. LeBlanc · Longmont, US
• Vincent P. Eck · Loveland, US
• Stephen W. Trynosky · Boca Raton, US
• Jeffrey V. Lindholm · Longmont, US
• Trevor J. Bauer · Campbell, US

Key dates

• Filing date: Dec 13, 2002
• Grant date: Jun 14, 2005
• Expiry date: Dec 25, 2022

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F15/7867
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A programmable logic device, such as a field programmable gate array, is partially reconfigured using a read-modify-write scheme that is controlled by a processor. The partial reconfiguration includes (1) loading a base set of configuration data values into a configuration memory array of the programmable logic device, thereby configuring the programmable logic device; (2) reading a first frame of configuration data values from the configuration memory array; (3) modifying a subset of the configuration data values in the first frame of configuration data values, thereby creating a first modified frame of configuration data values; and (4) overwriting the first frame of configuration data values in the configuration memory array with the first modified frame of configuration data values, thereby partially reconfiguring the programmable logic device. The steps of reading, modifying and overwriting are performed under the control of a processor.