Etch thinning techniques for wafer-to-wafer vertical stacks
US6908565B2 · kind B2 · utility
228Cited by
2References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 24, 2002 |
| Grant date | Jun 21, 2005 |
| Priority date | — |
| Expiry date | May 9, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for thinning wafer-to-wafer vertical stacks in the fabrication of stacked microelectronic devices. The methods include etching away unsupported portions of a wafer to be thinned in the vertical stack. The removal of the unsupported portions substantially eliminates potential cracking and chipping of the wafer, which can occur during the thinning process when the unsupported portions exist.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.