Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
US6908845B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2002 |
| Grant date | Jun 21, 2005 |
| Priority date | — |
| Expiry date | Nov 2, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The opening is initially fabricated in an upper surface of a wafer substrate, which allows for the use of alignment features on the upper surface of the wafer substrate. The openings are then filled with plugs. An integrated circuit is then manufactured over the upper surface of the substrate and the plugs. The plugs are located below the integrated circuit and do not take up “real estate” reserved for metal layers of the integrated circuit. A carrier is then bonded to an upper surface of the integrated circuit, whereafter a lower portion of the wafer substrate is removed in a grinding and etching operation. The plugs are then removed through a lower surface of the wafer substrate, whereafter the openings are filled with conductive members in a plating operation. A metal redistribution layer can be formed on a lower surface of the wafer substrate, because the carrier provides sufficient rigidity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.