Method for manufacturing sidewall contacts for a chalcogenide memory device
US6909107B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2004 |
| Grant date | Jun 21, 2005 |
| Priority date | — |
| Expiry date | Apr 26, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8418
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing sidewall contacts for a chalcogenide memory device is disclosed. A first conductive layer is initially deposited on top of a first oxide layer. The first conductive layer is then patterned and etched using well-known processes. Next, a second oxide layer is deposited on top of the first conductive layer and the first oxide layer. An opening is then etched into at least the first oxide layer such that a portion of the first conductive layer is exposed within the opening. The exposed portion of the first conductive layer is then removed from the opening such that the first conductive layer is flush with an inner surface or sidewall of the opening. After depositing a chalcogenide layer on top of the second oxide layer, filling the opening with chalcogenide, a second conductive layer is deposited on top of the chalcogenide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.