Jon Maimon
19Patents
9h-index
15Co-inventors
65Inventor score
Filing activity: Nov 15, 2000 → Aug 24, 2011
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6613604B2 | Method for making small pore for use in programmable resistance memory element | Electricity | 423 | Expired |
| US6589714B2 | Method for making programmable resistance memory element using silylated photoresist | Electricity | 384 | Expired |
| US6909107B2 | Method for manufacturing sidewall contacts for a chalcogenide memory device | Electricity | 195 | Expired |
| US6750079B2 | Method for making programmable resistance memory element | Physics | 157 | Expired |
| US6972428B2 | Programmable resistance memory element | Physics | 125 | Expired |
| US6815266B2 | Method for manufacturing sidewall contacts for a chalcogenide memory device | Electricity | 19 | Expired |
| US6733956B2 | Method for making programmable resistance memory element | Electricity | 16 | Expired |
| US7045383B2 | Method for making tapered opening for programmable resistance memory element | Electricity | 15 | Expired |
| US6774387B2 | Programmable resistance memory element | Physics | 12 | Expired |
| US6468860B1 | Integrated circuit capable of operating at two different power supply voltages | Electricity | 7 | Expired |
| US6927093B2 | Method for making programmable resistance memory element | Physics | 7 | Expired |
| US8009455B2 | Programmable resistance memory | Physics | 6 | Active |
| US8908413B2 | Programmable resistance memory | Physics | 2 | Active |
| US7365354B2 | Programmable resistance memory element and method for making same | Physics | 2 | Expired |
| US6638832B2 | Elimination of narrow device width effects in complementary metal oxide semiconductor (CMOS) devices | Electricity | 2 | Expired |
| US8217379B2 | Arsenic-containing variable resistance materials | Emerging Cross-Sectional Technologies | 0 | Active |
| US7906772B2 | Memory device | Emerging Cross-Sectional Technologies | 0 | Active |
| US8440501B2 | Memory device | Emerging Cross-Sectional Technologies | 0 | Active |
| US6750085B1 | Method for manufacturing sidewall contacts for a chalcogenide memory device | General | 0 | Revoked |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.