Low loss interconnect structure for use in microelectronic circuits
US6909127B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2001 |
| Grant date | Jun 21, 2005 |
| Priority date | — |
| Expiry date | Jun 27, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A low loss on-die interconnect structure includes first and second differential signal lines on one of the metal layers of a microelectronic die. One or more traces may also be provided on another metal layer of the die that are non-parallel (e.g., orthogonal) to the differential signal lines. Because the traces are non-parallel, they provide a relatively high impedance return path for signals on the differential signal lines. Thus, a signal return path through the opposite differential line predominates for the signals on the differential lines. In one application, the low loss interconnect structure is used within an on-die salphasic clock distribution network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.