Mark A. Anders
61Patents
11h-index
46Co-inventors
78Inventor score
Filing activity: Dec 23, 1998 → Dec 4, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9104474B2 | Variable precision floating point multiply-add circuit | Physics | 68 | Active |
| US10474458B2 | Instructions and logic to perform floating-point and integer operations for machine learning | Physics | 40 | Active |
| US10353706B2 | Instructions and logic to perform floating-point and integer operations for machine learning | Physics | 40 | Active |
| US11360767B2 | Instructions and logic to perform floating point and integer operations for machine learning | Physics | 33 | Active |
| US11080046B2 | Instructions and logic to perform floating point and integer operations for machine learning | Physics | 33 | Active |
| US11169799B2 | Instructions and logic to perform floating-point and integer operations for machine learning | Physics | 31 | Active |
| US7509368B2 | Sparse tree adder circuit | Physics | 25 | Active |
| US6628143B2 | Full-swing source-follower leakage tolerant dynamic logic | Electricity | 18 | Expired |
| US8284766B2 | Multi-core processor and method of communicating across a die | Emerging Cross-Sectional Technologies | 17 | Active |
| US6909127B2 | Low loss interconnect structure for use in microelectronic circuits | Electricity | 15 | Expired |
| US7154300B2 | Encoder and decoder circuits for dynamic bus | Electricity | 13 | Expired |
| US6225826A | Single ended domino compatible dual function generator circuits | Electricity | 11 | Expired |
| US7519646B2 | Reconfigurable SIMD vector processing system | Physics | 10 | Active |
| US9652425B2 | Method, apparatus and system for a source-synchronous circuit-switched network on a chip (NOC) | Emerging Cross-Sectional Technologies | 10 | Active |
| US6522186B2 | Hierarchical clock grid for on-die salphasic clocking | Physics | 9 | Expired |
| US6351150B1 | Low switching activity dynamic driver for high performance interconnects | Electricity | 8 | Expired |
| US9979668B2 | Combined guaranteed throughput and best effort network-on-chip | Emerging Cross-Sectional Technologies | 7 | Active |
| US7380099B2 | Apparatus and method for an address generation circuit | Physics | 7 | Expired |
| US9680765B2 | Spatially divided circuit-switched channels for a network-on-chip | Electricity | 6 | Active |
| US7352209B2 | Voltage-level converter | Electricity | 6 | Expired |
| US10599429B2 | Variable format, variable sparsity matrix multiplication instruction | Physics | 4 | Active |
| US7161992B2 | Transition encoded dynamic bus circuit | Electricity | 4 | Expired |
| US6614279B2 | Clock receiver circuit for on-die salphasic clocking | Physics | 3 | Expired |
| US7196548B2 | Single ended current-sensed bus with novel static power free receiver circuit | Electricity | 3 | Expired |
| US7325024B2 | Adder circuit with sense-amplifier multiplexer front-end | Physics | 3 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.