Lateral double-diffused MOS transistor having multiple current paths for high breakdown voltage and low on-resistance
US6909143B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2004 |
| Grant date | Jun 21, 2005 |
| Priority date | — |
| Expiry date | Apr 2, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/393
Abstract
A lateral double-diffused MOS (LDMOS) transistor is provided. The LDMOS transistor includes a semiconductor substrate 202 formed of a material having p-conductivity type impurities, a drift region formed of a material having n-conductivity type impurities on the semiconductor substrate, a first buried layer 206 of p-type material and a second buried layer 208 formed of n-type material. Layers 206 and 208 are arranged at the boundary between the semiconductor substrate and the drift region. A first well region 210 of p-type material contacts the first buried layer 206 n-type in a first portion 1 of the drift region. A first source region 214 conductivity in a predetermined upper region of the first well region, a drain region formed of a material having second conductivity type impurities in a predetermined region of the drift region, the drain region being spaced a predetermined gap apart from the first well region, a third buried layer formed of a material having first conductivity type impurities in a second region of the drift region, the third buried layer being overlapped with a part of an upper portion of the first buried layer, a second well region formed of a material havin…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.