High density DRAM with reduced peripheral device area and method of manufacture
US6909152B2 · kind B2 · utility
1Cited by
9References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 14, 2002 |
| Grant date | Jun 21, 2005 |
| Priority date | — |
| Expiry date | Dec 2, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/05
Abstract
A dynamic random access memory (DRAM) structure having a distance less than 0.14 μm between the contacts to silicon and the gate conductor is disclosed. In addition a method for forming the structure is disclosed, which includes forming the DRAM array contacts and the contacts to silicon simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.