Nonvolatile memory having bit line discharge, and method of operation thereof
US6909639B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2003 |
| Grant date | Jun 21, 2005 |
| Priority date | — |
| Expiry date | May 22, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The problem of bit disturb is reduced by discharging the floating bit lines of a nonvolatile memory array during programming. An illustrative virtual ground memory array uses single transistor floating gate type memory cells that are programmed using Fowler-Nordheim (“FN”) tunneling, highly conductive and lengthy bit lines, buried and relatively short sub-bit lines and a programming discharge circuit for controlling spurious voltages on the bit lines that can arise when some of the bit lines are left floating during programming. Discharge control transistor respectively coupled to the bit lines direct current into a discharge section. A discharge section may be provided for each bit line, or shared by all bit lines. The discharge section may be a fixed circuit section for use through the programming process or may be selected from multiple discharge options.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.