Pseudostatic memory circuit
US6909657B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2003 |
| Grant date | Jun 21, 2005 |
| Priority date | — |
| Expiry date | Sep 30, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/40611
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A psuedostatic memory circuit is selected by a memory selection signal. A control circuit, in a first operating mode, carries out a refresh of the memory area at a refresh address after reception of the refresh request signal by generation of a refresh signal if the memory circuit is deselected or if, in the event of selection of the memory circuit by the memory selection signal, the access to the memory area is ended before the generation of a further refresh request signal. The control circuit, in a second operating mode, interrupts an access to the memory area for the writing and read-out of data and carries out a refresh of the memory area by generation of a refresh signal if the memory circuit is selected and a further refresh request signal is received before the ending of the access to the memory area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.