Pipelined data processor with signal-initiated power management control
US6910141B2 · kind B2 · utility
7Cited by
104References
130Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2004 |
| Grant date | Jun 21, 2005 |
| Priority date | — |
| Expiry date | Feb 23, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pipelined data processor with signal-initiated power management control in which a plurality of subcircuits, including pipeline subcircuitry, and circuitry for generating and controlling at least one clock signal are responsive to at least one control signal by disabling a clock signal to the pipeline subcircuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.