Method for fabricating an IC interconnect system including an in-street integrated circuit wafer via
US6910268B2 · kind B2 · utility
156Cited by
28References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 27, 2001 |
| Grant date | Jun 28, 2005 |
| Priority date | — |
| Expiry date | Jul 21, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Vertical holes are created in streets separating individual integrated circuit (IC) dies formed on a semiconductor wafer, the holes spanning saw-lines along which the wafer is to be later cut to separate the IC die from one another to form individual IC chips. The holes are then filled with conductive material. After the wafer is cut along the saw-lines, portions of the conductive material on opposing sides of the saw-lines remain on peripheral edges of the IC chip to form signal paths between the upper and lower surfaces of the IC chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.