Method of forming dual damascene interconnection using low-k dielectric
US6911397B2 · kind B2 · utility
25Cited by
9References
16Claims
0Family size
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Key dates
| Filing date | Apr 11, 2003 |
| Grant date | Jun 28, 2005 |
| Priority date | — |
| Expiry date | Dec 25, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a dual damascene interconnection employs a low-k dielectric organic polymer as an insulating layer. With only one hard mask layer, ashing damage to the insulating layer is prevented using a hard mask layer and an etch-stop layer that are different in etch rate from that of a self-aligned spacer. Further, it is possible to form a via hole that is smaller than the resolution limit of the photolithographic process. As a result, the process is simplified and a photoresist tail phenomenon does not occur.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.