Transistor having insulating spacers on gate sidewalls to reduce overlap between the gate and doped extension regions of the source and drain

US6911695B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Shafqat Ahmed · Beaverton, US
• Henry Chao · Danville, US
• Derchang Kau · Cupertino, US

Key dates

• Filing date: Sep 19, 2002
• Grant date: Jun 28, 2005
• Expiry date: Sep 19, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/021

Abstract

A transistor comprising a gate, a channel beneath the gate and separated from the gate by an insulator, a source adjacent to the channel on a first side of the gate, a drain adjacent to the channel on a second side of the gate, doped extension regions into the channel from the source and the drain that underlap the gate, and insulating spacers adjacent to sidewalls of the gate that overlap the extension regions. The insulating spacers may be used to align the doped extension regions, offset the extension regions from the gate, and reduce Miller capacitance and standby leakage current.