Apparatus for functional and stress testing of exposed chip land grid array devices

US6911836B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Lonnie J. Cannon · Austin, US
• John Saunders Corbin, Jr. · Austin, US
• David L. Gardell · Saint Albans, US
• Jose Arturo Garza, Jr. · Pflugerville, US
• Jeffrey Frank Kutner · Pleasant Valley, US
• Kenneth Carl Larsen · Georgetown, US
• Howard Victor Mahaney, Jr. · Cedar Park, US
• John Joseph Salazar · Austin, US

Key dates

• Filing date: Aug 21, 2003
• Grant date: Jun 28, 2005
• Expiry date: Aug 21, 2023

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/2891
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A chip testing system with improved thermal performance. In a preferred embodiment, a nest assembly of a chip testing apparatus includes tooling balls and a fitted frame for improving alignment of a coldplate and a chip surface. In preferred embodiments, the coldplate is of unibody design. Thermal performance is also improved by balancing the forces exerted on the coldplate using an adjustable hose mounting bracket. The bracket allows the forces exerted by the hoses on the coldplate to be adjusted so they balance and cancel other unwanted forces on the cold plate.