Data transfer device for transferring data between blocks of different clock domains
US6911843B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jan 28, 2003 |
| Grant date | Jun 28, 2005 |
| Priority date | — |
| Expiry date | Mar 14, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M9/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The number of pulses of a clock signal CLK-A is circularly counted in a count range from “0” to “7”, and count signals indicating count values are produced. A clock signal CLK-B having a frequency lower than that of the clock signal CLK-A is produced from count signals of “3” and “7”, and data transfer between a high speed operating block operated in synchronization with the clock signal CLK-A and a low speed operating block operated in synchronization with the clock signal CLK-B is performed in synchronization with the clock signal CLK-B to receive input serial data or transmit output serial data. When a stuff bit of universal Serial Bus is detected in the input serial data or is inserted in the output serial data, a cycle of the clock signal CLK-B is lengthened by one cycle of the clock signal CLK-A.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.