Methods and apparatus for pipelined bus
US6912608B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2002 |
| Grant date | Jun 28, 2005 |
| Priority date | — |
| Expiry date | May 16, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for a pipelined bus which provides a very high performance interface to computing elements, such as processing elements, host interfaces, memory controllers, and other application-specific coprocessors and external interface units. The pipelined bus is a robust interconnected bus employing a scalable, pipelined, multi-client topology, with a fully synchronous, packet-switched, split-transaction data transfer model. Multiple non-interfering transfers may occur concurrently since there is no single point of contention on the bus. An aggressive packet transfer model with local conflict resolution in each client and packet-level retries allows recovery from collisions and buffer backups. Clients are assigned unique IDs, based upon a mapping from the system address space allowing identification needed for quick routing of packets among clients.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.