Shared bypass bus structure
US6912612B2 · kind B2 · utility
64Cited by
8References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2003 |
| Grant date | Jun 28, 2005 |
| Priority date | — |
| Expiry date | Dec 18, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0862
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A shared bypass bus structure for low-latency coherency controller access in a coherent scalable switch. In a coherent scalable switch with multiple coherent interconnect ports, distributed coherency control structures, and a crossbar interface between them, a shared bypass bus permits data transfer between the coherent interconnect ports and the coherency control structures while bypassing the crossbar interface. Some embodiments may comprise scalable switches to support one or more sets of processors with substantially independent snoop or cache coherency paths or arrangements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.