Kai Cheng
45Patents
11h-index
78Co-inventors
78Inventor score
Filing activity: Aug 6, 1998 → Mar 25, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7644347B2 | Silent data corruption mitigation using error correction code with embedded signaling fault detection | Physics | 69 | Active |
| US6912612B2 | Shared bypass bus structure | Physics | 64 | Expired |
| US6810467B1 | Method and apparatus for centralized snoop filtering | Physics | 44 | Expired |
| US6937473B2 | Heatsink device and method | Emerging Cross-Sectional Technologies | 33 | Expired |
| US7058750B1 | Scalable distributed memory and I/O multiprocessor system | Physics | 25 | Expired |
| US6959364B2 | Partially inclusive snoop filter | Physics | 22 | Expired |
| US6112283A | Out-of-order snooping for multiprocessor computer systems | Physics | 18 | Expired |
| US9600416B2 | Apparatus and method for implementing a multi-level memory hierarchy | Emerging Cross-Sectional Technologies | 18 | Active |
| US7234029B2 | Method and apparatus for reducing memory latency in a cache coherent multi-node architecture | Physics | 17 | Expired |
| US6857048B2 | Pseudo least-recently-used (PLRU) replacement method for a multi-node snoop filter | Physics | 15 | Expired |
| US7734980B2 | Mitigating silent data corruption in a buffered memory module architecture | Electricity | 14 | Active |
| US7984250B2 | Dynamic updating of thresholds in accordance with operating conditons | Physics | 11 | Active |
| US6636962B1 | Self-initializing chipset | Physics | 10 | Expired |
| US7093079B2 | Snoop filter bypass | Physics | 10 | Expired |
| US7343442B2 | Scalable distributed memory and I/O multiprocessor systems and associated methods | Physics | 8 | Active |
| US9141166B2 | Method, apparatus, and system for energy efficiency and energy conservation including dynamic control of energy consumption in power domains | Physics | 8 | Active |
| US7930464B2 | Scalable memory and I/O multiprocessor systems | Physics | 8 | Active |
| US7996625B2 | Method and apparatus for reducing memory latency in a cache coherent multi-node architecture | Physics | 7 | Active |
| US6915370B2 | Domain partitioning in a multi-node system | Physics | 5 | Expired |
| US7581068B2 | Exclusive ownership snoop filter | Physics | 4 | Active |
| US7617329B2 | Programmable protocol to support coherent and non-coherent transactions in a multinode system | Physics | 4 | Expired |
| US7603508B2 | Scalable distributed memory and I/O multiprocessor systems and associated methods | Physics | 3 | Active |
| US10241912B2 | Apparatus and method for implementing a multi-level memory hierarchy | Emerging Cross-Sectional Technologies | 2 | Active |
| US8527836B2 | Rank-specific cyclic redundancy check | Electricity | 2 | Active |
| US9391637B2 | Error correcting code scheme utilizing reserved space | Emerging Cross-Sectional Technologies | 2 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.