N-way set-associative external cache with standard DDR memory devices
US6912628B2 · kind B2 · utility
45Cited by
4References
42Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 22, 2002 |
| Grant date | Jun 28, 2005 |
| Priority date | — |
| Expiry date | Jan 22, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, cache system, and cache controller are provided. A two-way and n-way cache organization scheme are presented as at least two embodiments of a set-associative external cache that utilizes standard burst memory devices such as DDR (double data rate) memory devices. The set-associative cache organization scheme is designed to fully utilize burst efficiencies during snoop and invalidation operations. Cache lines are interleaved in such a way that a first burst transfer from the cache to the cache controller brings in a plurality of tags.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.