Scheme to encode predicted values into an instruction stream/cache without additional bits/area
US6912649B2 · kind B2 · utility
15Cited by
2References
23Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 13, 2002 |
| Grant date | Jun 28, 2005 |
| Priority date | — |
| Expiry date | Jun 26, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/382
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, articles of manufacture and systems for encoding an instruction are provided, whereby available bits within the instruction can be indicated for use. The available bits may include zero bits and constant bits. In one embodiment available bits include any bits within an expanded word that are not necessary for the execution of an instruction contained in the word. In another embodiment, bits are made available by reformatting/re-encoding a word, whereby the number of bits of some fields is abbreviated to a lesser number of bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.