Fin-based double poly dynamic threshold CMOS FET with spacer gate and method of fabrication
US6913960B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2004 |
| Grant date | Jul 5, 2005 |
| Priority date | — |
| Expiry date | May 11, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a dynamic threshold (DT) CMOS FET and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention provides a DT CMOS FET with a short, low resistance connection between the gate and the body and with low body-source/drain capacitance. The low body-source/drain capacitance is achieved using a thin, fin-type body. The low resistance connection between the gate and the body contact is achieved by having the gate and body contact aligned on opposite long sides of the fin with a bridge over the top of the narrow fin electrically connecting the gate and body.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.