Flash memory device structure and manufacturing method thereof
US6913974B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2004 |
| Grant date | Jul 5, 2005 |
| Priority date | — |
| Expiry date | May 17, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A flash memory device structure is provided. The flash memory device consists of a P-type substrate with an opening, a deep N-well region in the P-type substrate, a first gate structure and a second gate structure on the respective sidewalls of the opening, an insulating layer in the space between the first gate structure and the second gate structure, a source region in the P-type substrate at the bottom section of the opening, a drain region in the P-type substrate at the top section of the opening, a P-well region in the deep N-well region such that the junction between the P-well and the deep N-well region is at a level higher than the bottom section of the opening and a P-type pocket doping region in the P-type substrate on the sidewalls of the opening such that the P-type pocket doping region connects the P-well region with the source region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.