EEPROM and EEPROM manufacturing method
US6914288B2 · kind B2 · utility
10Cited by
6References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2003 |
| Grant date | Jul 5, 2005 |
| Priority date | — |
| Expiry date | Sep 12, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6891
Abstract
A memory transistor of an EEPROM has a floating gate electrode of a shape such that it covers the entirety of a tunnel film and a channel region and does not cover a region between the channel region and an embedded layer. And, a control gate electrode is formed on an interlayer insulating film on the floating gate electrode into a shape such that it is wider than the floating gate electrode above the tunnel film, and is narrower than the floating gate electrode above the channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.