Adaptive keeper sizing for dynamic circuits based on fused process corner data
US6914452B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2002 |
| Grant date | Jul 5, 2005 |
| Priority date | — |
| Expiry date | Mar 8, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0963
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An invention is provided for an adaptive keeper circuit. The adaptive keeper circuit includes a first keeper transistor having a first terminal in electrical communication with a power supply and a second terminal in electrical communication with an internal dynamic node. In addition, a second keeper transistor is included that is configured in parallel to the first keeper transistor. The second keeper transistor also has a first terminal in electrical communication with the power supply. The second keeper transistor can be added to the first keeper transistor using a feedback bit line, which is configured to control current flow between the second keeper transistor and the internal dynamic node based on a state of the feedback bit line. The state of the feedback bit line is based on a process corner characteristic of the die. Additional keeper transistors and corresponding feedback bit lines can be added to the keeper circuit to increase flexibility.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.