Register controlled DLL for reducing current consumption
US6914798B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2004 |
| Grant date | Jul 5, 2005 |
| Priority date | — |
| Expiry date | Jun 14, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00104
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A register controlled delay locked loop (DLL) usable in a semiconductor device is provided. The register controlled delay locked loop includes an internal clock generating unit generating a delayed clock signal and a reference clock signal, a first delay unit compensating for an amount of delay caused by a signal transmission path of the delayed clock signal, a phase comparator detecting a difference between the reference clock signal and the delayed clock signal and thereby generating a detection signal, a controller having a plurality of second delay units for controlling an amount of delay of the delayed clock signal in response to the detection signal, a driver driving a DLL clock signal, and an enable signal generator enabling the driver in response to an activation or non-activation signal of the semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.