Erasing storage nodes in a bi-directional nonvolatile memory cell
US6914820B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 30, 2004 |
| Grant date | Jul 5, 2005 |
| Priority date | — |
| Expiry date | Sep 30, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory transistor having a pair of separate floating gates overlying end regions of a channel and a control gate that overlies the floating gates and a central region of the channel effectively operates as a pair of floating gate transistors with an intervening select transistor. Each floating gate can be charged to store a distinct binary, analog, or multi-bit value. An erase operation can use a negative voltage on the control and a positive voltage on an underlying well or source/drain region to cause tunneling that discharges one or both floating gates. Applying a limited current to a source/drain region during an erase operation can cause the source/drain region and a floating gate to rise together and avoid band-to-band tunneling and resulting hole injection into the floating gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.