Integrating chip scale packaging metallization into integrated circuit die structures
US6917105B2 · kind B2 · utility
7Cited by
1References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 3, 2003 |
| Grant date | Jul 12, 2005 |
| Priority date | — |
| Expiry date | Jul 2, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Wafer-level chip-scale packaging technology is used for improving performance or reducing size of integrated circuits by using metallization of pad-to-bump-out beams as part of the integrated circuit structure. Chip-scale packaging under bump metal is routed to increase the thickness of top metal of the integrated circuit, increasing current carrying capability and reducing resistance. An exemplary embodiment for a power MOSFET array integrated structure is described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.