Method and structure for read prefetch in a storage complex architecture
US6917990B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2002 |
| Grant date | Jul 12, 2005 |
| Priority date | — |
| Expiry date | Feb 20, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0689
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and associated structure for improving storage system performance by reducing latency associated with communication medium transactions internal to a storage subsystem. In one aspect of the present invention, an I/O control element associated with a storage system transmits prefetch read requests to an associated storage element of the storage system in response to receipt of a host system request. This allows the storage element to commence data transfer to the I/O element in advance of the I/O element returning the data to the host system. Subsequent transfers of data from the storage element to the I/O element then overlap the transfer of data from the I/O element to the host. In another specific aspect of the present invention, methods and associated structures eliminate latency associated with PCI-X bus split transactions between the front-end (host interface portion) of the I/O element and the back-end (storage element interface) of the I/O element by overlapping the transfer of prefetched data to the host system with continued fetching of subsequent data from the storage element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.