Scalable directory based cache coherence protocol
US6918015B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2003 |
| Grant date | Jul 12, 2005 |
| Priority date | — |
| Expiry date | Mar 31, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method is disclosed to maintain the coherence of shared data in cache and memory contained in the nodes of a multiprocessing computer system. The distributed multiprocessing computer system contains a number of processors each connected to main memory. A processor in the distributed multiprocessing computer system is identified as a Home processor for a memory block if it includes the original memory block and a coherence directory for the memory block in its main memory. An Owner processor is another processor in the multiprocessing computer system that includes a copy of the Home processor memory block in a cache connected to its main memory. Whenever an Owner processor is present for a memory block, it is the only processor in the distributed multiprocessing computer system to contain a copy of the Home processor memory block. Eviction of a memory block copy held by an Owner processor in its cache requires a write of the memory block copy to its Home and update of the corresponding coherence directory. No reads of the Home processor directory or modification of other processor cache and main memory is required. The coherence controller in each processor is able to s…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.