Apparatus and methods for determining critical area of semiconductor design data
US6918101B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2002 |
| Grant date | Jul 12, 2005 |
| Priority date | — |
| Expiry date | Nov 28, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are mechanisms for efficiently and accurately calculating critical area. In general terms, a method for determining a critical area for a semiconductor design layout is disclosed. The critical area is utilizable to predict yield of a semiconductor device fabricated from such layout. A semiconductor design layout having a plurality of features is first provided. The features have a plurality of polygon shapes which include nonrectangular polygon shapes. Each feature shape has at least one attribute or artifact, such as a vertex or edge. A probability of fail function is calculated based on at least a distance between two feature shape attributes or artifacts. By way of example implementations, a distance between two neighboring feature edges (or vertices) or a distance between two feature edges (or vertices) of the same feature is first determined and then used to calculate the probability of fail function. In a specific aspect, the distances are first used to determine midlines between neighboring features or midlines within a same feature shape, and the midlines are then used to determine the probability of fail function. A critical area of the design layout is then dete…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.