System and method for scheduling instructions to maximize outstanding prefetches and loads
US6918111B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2000 |
| Grant date | Jul 12, 2005 |
| Priority date | — |
| Expiry date | Jan 22, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/4442
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a method and device for ordering memory operation instructions in an optimizing compiler. for a processor that can potentially enter a stall state if a memory queue is full. The method uses a dependency graph coupled with one or more memory queues. The dependency graph is used to show the dependency relationships between instructions in a program being compiled. After creating the dependency graph, the ready nodes are identified. Dependency graph nodes that correspond to memory operations may have the effect of adding an element to the memory queue or removing one or more elements from the memory queue. The ideal situation is to keep the memory queue as full as possible without exceeding the maximum desirable number of elements, by scheduling memory operations to maximize the parallelism of memory operations while avoiding stalls on the target processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.