Method for fabricating ferroelectric random access memory device with merged-top electrode-plateline capacitor
US6919212B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2003 |
| Grant date | Jul 19, 2005 |
| Priority date | — |
| Expiry date | Dec 18, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/688
Abstract
The present invention relates to a method for fabricating a ferroelectric random access memory (FeRAM) device. The method includes the steps of: forming a first inter-layer insulation layer on a substrate; forming a storage node contact connected with a partial portion of the substrate by passing through the first inter-layer insulation layer; forming a lower electrode connected to the storage node contact on the first inter-layer insulation layer; forming a second inter-layer insulation layer having a surface level lower than that of the lower electrode so that the second inter-layer insulation layer encompasses a bottom part of the lower electrode; forming an impurity diffusion barrier layer encompassing an upper part of the lower electrode on the second inter-layer insulation layer; forming a ferroelectric layer on the lower electrode and the impurity diffusion barrier layer; and forming a top electrode on the ferroelectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.