Interconnect structure for an integrated circuit and method of fabrication
US6919637B2 · kind B2 · utility
16Cited by
1References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2002 |
| Grant date | Jul 19, 2005 |
| Priority date | — |
| Expiry date | Sep 30, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An interconnect structure for an integrated circuit having several levels of conductors is disclosed. Dielectric pillars for mechanical support are formed between conductors in adjacent layers at locations that do not have vias. The pillars are particularly useful with low-k ILD or air dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.