Circuit arrangement for low-noise fully differential amplification
US6919767B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2001 |
| Grant date | Jul 19, 2005 |
| Priority date | — |
| Expiry date | Jan 16, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/45654
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention relates to a circuit for low noise, fully differential amplification. A feedback signal (121) is detected in a differential output step of the differential amplification circuit by means of a voltage distributor formed by a first feedback resistance (119) and a second feedback resistance (120). A first output signal (111) is provided at a first output circuit node (117) and a second output signal (112) is provided at a second output circuit node (118). The respective first and second output signals (111) or (112) form a full output signal which corresponds to an input signal formed by a first and a second input signal (101) or (102). A load current (134), an input current (132) and a reference current (132) are established by means of a load current source (128), an input current source (131) and a reference current source (127). A matching transistor (301) is used to adjust an adaptation between the load current source (128), the input current source (131) and the reference current source (127). A feedback signal (121) of the differential amplification circuit is compared with a reference voltage (122) in a reference step, and the load current (134) is mirrored in th…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.