Successive approximation analog/digital converter with reduced chip area
US6919837B2 · kind B2 · utility
5Cited by
4References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2004 |
| Grant date | Jul 19, 2005 |
| Priority date | — |
| Expiry date | Jul 21, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/46
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A successive approximation A/D converter includes first and second S/H and comparators sampling and holding first and second external analog input voltages simultaneously and comparing the held, first and second external analog input voltages with a reference voltage to output first and second signals having levels corresponding to resultant comparisons, and a reference voltage generator operative in response to the first and second signals to generate the reference voltage. The two S/H and comparators share the single reference voltage generator. A reduced chip area can be achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.