Integrated circuit embedded with single-poly non-volatile memory
US6920067B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 25, 2002 |
| Grant date | Jul 19, 2005 |
| Priority date | — |
| Expiry date | Aug 5, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system on chip (SOC) contains a core circuit and an input/output (I/O) circuit embedded with an array of single-poly erasable programmable read only memory cells, each of which comprises a first PMOS transistor serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P-type substrate. The first PMOS transistor includes a single-poly floating gate, a first P+ doped drain region and a first P+ doped source region, the second PMOS transistor includes a single-poly select gate and a second P+ doped source region, and the first P+ doped source region of the first PMOS transistor serves as a drain of the second PMOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.