Apparatus for latency specific duty cycle correction
US6920081B2 · kind B2 · utility
6Cited by
6References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 26, 2004 |
| Grant date | Jul 19, 2005 |
| Priority date | — |
| Expiry date | Jul 26, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The illustrated embodiments relate to a control circuit that is adapted to use a latency signal to generate an output signal. The latency is adapted to be used to create a control signal that is dependent on the latency signal. The control signal is adapted to be used to select from among multiple input sources. The selected input source is adapted to be used to create an output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.