Post plasma clean process for a hardmask
US6921721B2 · kind B2 · utility
3Cited by
4References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2003 |
| Grant date | Jul 26, 2005 |
| Priority date | — |
| Expiry date | Oct 24, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76224
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a process of manufacturing a semiconductor device that comprises a process of manufacturing a semiconductor device that includes plasma etching 250 through a patterned hardmask layer 210 located over a semiconductor substrate 225 wherein the plasma etching forms a modified layer 210a on the hardmask layer 210, and removing at least a substantial portion of the modified layer 210a by exposing the modified layer 210a to a post plasma clean process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.