Brian K. Kirkpatrick
51Patents
5h-index
60Co-inventors
75Inventor score
Filing activity: Dec 18, 1998 → May 16, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6720247B2 | Pre-pattern surface modification for low-k dielectrics using A H2 plasma | Electricity | 23 | Expired |
| US7838356B2 | Gate dielectric first replacement gate processes and integrated circuits therefrom | Electricity | 16 | Active |
| US8058161B2 | Recessed STI for wide transistors | Electricity | 13 | Active |
| US8372703B2 | Gate dielectric first replacement gate processes and integrated circuits therefrom | Electricity | 10 | Active |
| US6797644B2 | Method to reduce charge interface traps and channel hot carrier degradation | Electricity | 6 | Expired |
| US6287983A | Selective nitride etching with silicate ion pre-loading | Electricity | 5 | Expired |
| US7732284B1 | Post high-k dielectric/metal gate clean | Emerging Cross-Sectional Technologies | 5 | Active |
| US9070785B1 | High-k / metal gate CMOS transistors with TiN gates | Electricity | 4 | Active |
| US8043921B2 | Nitride removal while protecting semiconductor surfaces for forming shallow junctions | Electricity | 4 | Active |
| US7049242B2 | Post high voltage gate dielectric pattern plasma surface treatment | Electricity | 3 | Expired |
| US6921721B2 | Post plasma clean process for a hardmask | Electricity | 3 | Expired |
| US7018925B2 | Post high voltage gate oxide pattern high-vacuum outgas surface treatment | Electricity | 3 | Expired |
| US7943456B2 | Selective wet etch process for CMOS ICs having embedded strain inducing regions and integrated circuits therefrom | Electricity | 3 | Active |
| US6831008B2 | Nickel silicide—silicon nitride adhesion through surface passivation | Electricity | 3 | Expired |
| US9721847B2 | High-k / metal gate CMOS transistors with TiN gates | Electricity | 2 | Active |
| US7384869B2 | Protection of silicon from phosphoric acid using thick chemical oxide | Electricity | 2 | Expired |
| US8216945B2 | Wafer planarity control between pattern levels | Electricity | 1 | Active |
| US7504339B2 | Method to form shallow trench isolation with rounded upper corner for advanced semiconductor circuits | Electricity | 1 | Expired |
| US7927993B2 | Cross-contamination control for semiconductor process flows having metal comprising gate electrodes | Electricity | 1 | Active |
| US9490143B1 | Method of fabricating semiconductors | Electricity | 1 | Active |
| US7339240B2 | Dual-gate integrated circuit semiconductor device | Electricity | 1 | Expired |
| US8450221B2 | Method of forming MOS transistors including SiON gate dielectric with enhanced nitrogen concentration at its sidewalls | Electricity | 1 | Active |
| US8441078B2 | Semiconductor device including SiON gate dielectric with portions having different nitrogen concentrations | Electricity | 1 | Active |
| US6861348B2 | Pre-pattern surface modification of low-k dielectrics | Electricity | 1 | Expired |
| US8618661B2 | Die having coefficient of thermal expansion graded layer | Electricity | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.