Integrated circuit having a thin film resistor located within a multilevel dielectric between an upper and lower metal interconnect layer
US6921962B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 1999 |
| Grant date | Jul 26, 2005 |
| Priority date | — |
| Expiry date | Dec 2, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A thin film resistor (60) is contained between two metal interconnect layers (40, 100) of an integrated circuit. Contact may be made to the resistor (60) through vias (95) from the metal layer (100) above the resistor (60) to both the thin film resistor (60) and the underlying metal layer (40) simultaneously. The resistor (60) may include portions of a hard mask (70) under the vias (95) to protect the resistor material (60) during the via (95) etch. This design provides increased flexibility in fabricating the resistor (60) since processes, materials, and chemicals do not have to satisfy the conditions of both the resistor (60) and the rest of the integrated circuit (especially the interconnect layer 40) simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.