Method and apparatus for switching amplification having variable sample point and variable order correction
US6922100B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2003 |
| Grant date | Jul 26, 2005 |
| Priority date | — |
| Expiry date | Jul 29, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/2171
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method and/or apparatus for adjusting the sample time and order associated with a digital correction system for maximizing output power and minimizing power stage delay sensitivity of a switching power stage. In certain embodiments, the sample point of an ADC may be changed as a function of the duty ratio of the PWM signal thus allowing higher performance and use of less expensive power stage components. In addition, adjustment of the order of an integrating error amplifier in the system permits operation of the power stage with an output being permitted to saturate up to the power supply rails, thus increasing a power output of the power stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.