High performance SRAM device and method of powering-down the same
US6922370B2 · kind B2 · utility
12Cited by
4References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2003 |
| Grant date | Jul 26, 2005 |
| Priority date | — |
| Expiry date | Jan 15, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An SRAM device and a method of powering-down an SRAM device. In one embodiment, the SRAM device includes (1) an SRAM array coupled to an SRAM array low voltage source that provides a low SRAM array supply voltage VSB to the SRAM device and (2) main column peripheral circuitry having main pre-charge circuitry free of an SRAM header, coupled to the SRAM array by bit lines and coupled to a sleep mode controller through an associated main column peripheral driving circuitry that is configured to isolate the bit lines from a power supply during a sleep mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.