Method of power consumption reduction in clocked circuits
US6922818B2 · kind B2 · utility
10Cited by
9References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2001 |
| Grant date | Jul 26, 2005 |
| Priority date | — |
| Expiry date | Aug 7, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for reducing power consumption of a clocked circuit containing a plurality of latches is provided. A first latch, within the plurality of latches, is located which has more than a predetermined slack. The possibility of substituting an available second latch, that requires less power to operate, is then determined, subject to the constraint that the slack after substitution should still be positive, although it may be less than the predetermined number mentioned above. Where such a possibility is determined to exist, the first latch is then replaced with the available second latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.