Oxide/nitride stacked in FinFET spacer process
US6924178B2 · kind B2 · utility
35Cited by
13References
24Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 8, 2003 |
| Grant date | Aug 2, 2005 |
| Priority date | — |
| Expiry date | Dec 8, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
In a FinFET integrated circuit, the fins are formed with a body thickness in the body area and then thickened in the source/drain area outside the body to improve conductivity. The thickening is performed with epitaxial deposition while the gates are covered by a composite gate cover layer to prevent thickening of the gates, which may short the gate to the source/drain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.